This invention relates to manufacture of semiconductor devices, and more particularly to a dynamic read/write memory cell of the MOS VLSI type.
Semiconductor dynamic RAM devices of the type shown in U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine (a 16K RAM), or U.S. Pat. No. 4,293,993 issued to McAlexander, White and Rao (a 64K RAM), have been manufactured by processes of the type described in U.S. Pat. Nos. 4,055,444 or 4,388,121, both issued to G. R. M. Rao; all of these patents are assigned to Texas Instruments. In order to reduce the size of a dynamic RAM cell to the level needed to produce very high density RAMS, such as the 1-Megabit DRAM, various methods of reducing the capacitor size have been proposed. The magnitude of the capacitor must be maintained at not less than a certain value so that sufficient charge is stored. One method of reducing capacitor area yet maintaining adequate charge storage is to reduce the oxide thickness as explained in U.S. Pat. No. 4,240,092 issued to Kuo, assigned to Texas Instruments; this approach reaches a limit in the area of about 100 to 200 .ANG. oxide thickness because of yield and reliability problems. Another way of increasing the capacitance per unit area is to etch a groove, or trench, in the capacitor region, thus increasing the area; an example of this method is shown in U.S. Pat. No. 4,225,945, also assigned to Texas Instruments.
It is the principal object of this invention to provide an improved high density dynamic RAM cell, particularly with an increased capacitance area due to a trench etched into the storage capacitor region. Another object is to provide an improved method of making trench capacitor type dynamic RAM cells. A further object is to provide a simple and reliable process for forming trench capacitors.